1. Field of the Invention
The present invention relates to a discharge-lamp lighting apparatus for lighting a discharge lamp, and particularly, to a discharge-lamp lighting apparatus for lighting a cold cathode lamp installed in, for example, a liquid-crystal portable device.
2. Description of the Related Art
Discharge-lamp lighting apparatuses are classified into those employing n-type MOSFETs as high-side switching elements and those employing p-type MOSFETs as high-side switching elements. Liquid-crystal portable devices such as notebook computers employing cold cathode lamps usually use p-type MOSFETs as high-side switching elements because, if n-type MOSFETs are used as high-side switching elements, bootstrap circuits and the like are needed to drive the n-type MOSFETs, to complicate drive circuits and increase cost.
A capacitor boost technique is a simple example of driving a discharge-lamp lighting apparatus employing p-type MOSFETs as high-side switching elements. An example thereof is disclosed in Japanese Unexamined Patent Application Publication No. 2003-164163 shown in FIG. 1. In FIG. 1, first and second series circuits are arranged between a DC power source Vin and the grounding. The first series circuit includes a p-type MOSFET Qp1 serving as a high-side switching element and an n-type MOSFET Qn1 serving as a low-side switching element. The second series circuit includes a p-type MOSFET Qp2 serving as a high-side switching element and an n-type MOSFET Qn2 serving as a low-side switching element. Between a connection point of the p- and n-type MOSFETs Qp1 and Qn1 and a connection point of the p- and n-type MOSFETs Qp2 and Qn2, there is connected a series circuit consisting of a resonance capacitor C3 and a primary winding P of a transformer T. Each end of a secondary winding S of the transformer T is connected to a capacitor C4.
The DC power source Vin is connected to a source of the p-type MOSFET Qp1 (hereinafter referred to as p-type FET Qp1) and a source of the p-type MOSFET Qp2 (hereinafter referred to as p-type FET Qp2). Between the gate and source of the p-type FET Qp1, there is connected a parallel circuit consisting of a diode D1 and a resistor R1. Between the gate and source of the p-type FET Qp2, there is connected a parallel circuit consisting of a diode D2 and a resistor R2. The gate of the p-type FET Qp1 is connected through a capacitor C1 to a terminal PD1 of a control IC 1. The gate of the p-type FET Qp2 is connected through a capacitor C2 to a terminal PD2 of the control IC 1. The gate of the n-type MOSFET Qn1 (hereinafter referred to as n-type FET Qn1) is connected to a terminal ND1 of the control IC 1. The gate of the n-type MOSFET Qn2 (hereinafter referred to as n-type FET Qn2) is connected to a terminal ND2 of the control IC1.
The control IC1 (or a discrete circuit) includes a regulator 11, a frequency divider 13, an error amplifier 15, and an oscillator 17. The regulator 11 receives the DC power source Vin and generates a predetermined voltage Vp.REG, which is supplied to the frequency divider 13. A first end of the secondary winding S of the transformer T is connected to a first electrode of a discharge lamp 3. A second electrode of the discharge lamp 3 is connected to a lamp current detector 5. The lamp current detector 5 detects a current passing through the discharge lamp 3 and provides the error amplifier 15 with a voltage proportional to the detected current. The error amplifier 15 compares the voltage from the lamp current detector 5 with a reference voltage and sends an error voltage to the oscillator 17. The oscillator 17 compares the error voltage with a triangle wave and generates a pulse signal whose width corresponds to the error voltage. When the error voltage is large, the pulse width of the pulse signal is wide, and when the error voltage is small, the pulse width of the pulse signal is narrow.
The frequency divider 13 divides the frequency of the pulse signal from the oscillator 17. Namely, in a first half of a given period, a high-level pulse signal is supplied through the terminals PD1 and ND1 to the p- and n-type FETs Qp1 and Qn1 and a low-level pulse signal is supplied through the terminals PD2 and ND2 to the p- and n-type FETs Qp2 and Qn2. In a second half of the given period, a low-level pulse signal is supplied to the p- and n-type FETs Qp1 and Qn1 and a high-level pulse signal is supplied to the p- and n-type FETs Qp2 and Qn2. This results in alternating an ON-period in which the p-type FET Qp1 and n-type FET Qn2 are simultaneously turned on and an ON-period in which the p-type FET Qp2 and n-type FET Qn1 are simultaneously turned on.
Operation of the discharge-lamp lighting apparatus of FIG. 1 will be explained with reference to a timing chart of FIG. 2. At time t2, the p- and n-type FETs Qp1 and Qn2 are turned on to pass a current from the DC power source Vin along a route consisting of Qp1, C3, P, and Qn2, to apply a voltage to the capacitor C3 and the primary winding P of the transformer T. As a result, the capacitor C3 and an inductance of the primary winding P of the transformer T cause resonance to produce a sinusoidal wave current. The secondary winding S of the transformer T then generates a voltage to pass a current to the discharge lamp 3, thereby turning on the discharge lamp 3.
At time t3, the p- and n-type FETs Qp2 and Qn1 are turned on to pass a current from the DC power source Vin along a route consisting of Qp2, P, C3, and Qn1, to reversely apply a voltage to the capacitor C3 and the primary winding P of the transformer T. As a result, the secondary winding S of the transformer T generates a high sinusoidal wave voltage of opposite phase, to turn on the discharge lamp 3.
If the input voltage Vin suddenly varies due to, for example, the insertion or removal of an adaptor, the related art of FIG. 1 increases the gate-source voltage of each of the p-type FETs Qp1 and Qp2 without regard to the levels of drive signals from the terminals PD1 and PD2 and turns on the p-type FETs Qp1 and Qp2. As a result, a bridge circuit consisting of the four FETs Qp1, Qn1, Qp2, and Qn2 passes a shoot-through (short-circuit) current to break the p-type FETs Qp1 and Qp2. For example, if the input voltage Vin suddenly increases, charge currents pass through the capacitors C1 and C2, to increase the terminal voltages of the resistors R1 and R2, i.e., the gate-source voltages of the p-type FETs Qp1 and Qp2, thereby turning on the p-type FETs Qp1 and Qp2.
To cope with this problem, a bipolar totem pole technique is used to drive p-type FETs serving as high-side switching elements. FIG. 3 shows a discharge-lamp lighting apparatus disclosed in Japanese Unexamined Patent Application Publication No. 11-298308 employing the totem pole technique. FIG. 4 is a timing chart showing signals at various parts in the apparatus of FIG. 3. The apparatus of FIG. 3 has a control IC 1a that differs from the control IC1 of FIG. 1 in drivers for driving p-type FETs Qp1 and Qp2. In FIG. 3, the driver for driving the p-type FET Qp1 includes transistors Q1 to Q4 and resistors R0 to R4 and the driver for driving the p-type FET Qp2 includes transistors Q5 to Q8 and resistors R5 to R9.
If an input voltage Vin suddenly increases in FIG. 3, a voltage from the resistor R1 turns on the transistor Q1 to substantially zero the gate-source voltage of the p-type FET Qp1. Similarly, a voltage from the resistor R6 turns on the transistor Q5 to substantially zero the gate-source voltage of the p-type FET Qp2. Since the p-type FETs Qp1 and Qp2 are OFF, no shoot-through current passes through a bridge circuit.